As the semiconductor industry advances, the sizes of active semiconductor devices have shrunk to sub-micron dimensions. This has required the formation of devices that push the limits of current manufacturing processes, such as photolithography. Specifically, it is difficult to form submicron semiconductor devices having acceptable electrical characteristics using current manufacturing techniques.
Semiconductor devices formed with a narrow width (i.e. narrow width devices) are particularly affected by decreasing geometries. As an example, narrow width MOS transistors are difficult to fabricate with an acceptable threshold voltage or (Vt).
In a MOS transistor, the threshold voltage (Vt) is the voltage that must be applied to the gate region of the transistor before a current will flow in the channel under the gate region. In general, higher threshold voltages are undesirable because higher power supplies are required for operating the semiconductor devices. In addition, with higher threshold voltages, the semiconductor devices are slower. Moreover, if the threshold voltage (Vt) of an access device for a memory cell is too high, then it is more difficult to write data into the cell.
FIGS. 1A-1D illustrate the difficulty of forming narrow width access transistors with an acceptable threshold voltage in an SRAM cell. As shown in FIG. 1A, a semiconductor fabrication process begins with a silicon substrate 10. Depending on the circuit requirements, different conductivity regions such as n-wells or p-wells (not shown) may be formed on the substrate 10, by various well known processes. The substrate 10 is then-typically covered with a pad oxide 12. A silicon nitride mask 14 is then deposited on the substrate 10.
The silicon nitride mask 14 is photopatterned and etched in a predetermined pattern. After etching, and as shown in FIG. 1B, the silicon nitride mask 14 includes a pattern of solid areas 16, 18 and open areas 20. This pattern is repeated many times. The open areas 20 of the silicon nitride mask 14 expose the areas of the substrate 10 where future field isolation oxide will be formed. The solid areas 16, 18 of the silicon nitride mask 14 cover areas on the substrate 10 on which future active devices will be formed.
In an SRAM cell, the active devices may include access transistors formed with a narrow width. The width of such narrow width access transistors may be in the range of 0.4 to 1 .mu.m. Narrow width active devices, such as access transistors, will be formed under the narrow width solid areas 16 of the nitride mask 14. Conventional width active devices, such as the pulldown transistors for the SRAM cell, will be formed under the solid areas 18 of the nitride mask.
After formation of the silicon nitride mask 14 and as shown in FIG. 1C, a local oxidation of silicon process (LOCOS) is performed on the substrate 10. During the LOCOS process, a field oxide (FOX) 22 is formed on the substrate 10 in the open areas 20 (FIG. 1B) of the nitride mask 14. The field oxide 22 grows not only vertically in the exposed areas 20 of the substrate 10 but also laterally underneath the edges of the silicon nitride mask 14. This lateral encroachment under the silicon nitride mask 14 is known as the "bird's beak" 28.
Following the formation of the field oxide 22, the silicon nitride mask 14 is removed. Active semiconductor devices will be formed in active areas 24, 26 of the substrate 10 between the areas of field oxide 22. An SRAM cell may include narrow width active areas 24 and conventionally sized active areas 26.
Next, and as shown in FIG. 1D, the field oxide 22 is subjected to a local implanted field, or LIF step. During the LIF step a field implant dopant 34 is introduced into the field oxide 22 using ion implantation. In general, the LIF step is used to isolate individual active devices from one another.
For isolating NMOS devices, a p-type dopant such as boron is used as the field implant. For isolating PMOS devices, an n-type dopant such as phosphorus is used as the field implant. Implantation of the dopants during the LIF step is performed at an energy level that causes the field implant dopant 34 to penetrate through the field oxide 22 and enter the substrate 10. The peak concentration of the field implant dopant 34 into the substrate 10 is indicated in FIG. 1D by the dotted line 36.
During the LIF step, the active areas 24, 26 of the substrate 10 are protected from the field implant dopant 34 by a patterned layer of field implant photoresist 32. The field implant photoresist 32 is deposited and patterned using standard photolithographic techniques. This may include deposition of a photosensitive photoresist, followed by photopatterning using a reticle, and then developing.
With a high density SRAM cell, the width of the narrow width active area 24 is close to the minimum feature size for current photolithographic processes (e.g., 0.4 .mu.m to 1 .mu.m). It is difficult to precisely align the pattern of the field implant photoresist 32 with the pattern of the narrow width active areas 24. Any misalignment between the field implant photoresist 32 and the narrow width active areas 24 will leave the narrow width active areas 24 unprotected during the LIF step.
The threshold voltage (Vt) of a narrow width active device such as the access device for a memory cell, is very sensitive to the dopant concentration in the substrate 10. In a narrow width device, when the LIF is slightly misaligned, the region of the device that undesirably receives the LIF implant is a much larger percentage of the total device width than it is in wider devices. Thus, misalignment of the LIF and subsequent diffusion can cause the channel region of a narrow width device to have a much higher dopant concentration than the majority of the width in a wider device. Hence, the narrow device Vt increases. In general, a p-type field implant dopant, such as boron, will cause the threshold voltage (Vt) of an n-channel transistor to increase. Conversely, an n-type field implant dopant, such as phosphorus, will cause the threshold voltage (Vt) of an p-channel transistor to decrease.
The threshold voltage (Vt) of the active devices is also affected by diffusion of the field implanted dopant 32 under the bird's beaks 28 of the field oxide 22. Specifically, during various thermal cycles used in the semiconductor manufacturing process, the field implant dopant 32 may migrate under the narrow width active areas 24. As shown in FIG. 2, the field implant dopant 32 may diffuse into the future MOS device channel region 38. This diffusion is indicated by the dotted lines 40 in FIG. 2.
This unwanted diffusion of the field implant dopant 32 decreases the effective electrical width (W.sub.1) of the active area 24. The effective electrical width (W.sub.1) of the active area 24 is thus less than the actual width (W.sub.2) of the active area 24. As the effective electrical width (W.sub.1) of an access device approaches zero, the threshold voltage (Vt) of the access device increases due to field implant dopant diffusion into the channel region 38. This is also sometimes referred to as the "narrow width effect". This is an undesirable condition because as previously stated, a high threshold voltage (Vt) for an access device is undesirable.
In view of these shortcomings associated with the manufacture of semiconductor devices, there is a need in the art for improved methods for forming and tailoring the electrical characteristics of semiconductor devices and particularly narrow width devices with an acceptable threshold voltage (Vt). Additionally, there may be situations that arise in semiconductor circuit design where select devices other than narrow width devices may require non-standard threshold voltages (Vt). These special devices may need either a higher or a lower threshold voltage (Vt) from the nominal.
Accordingly, it is an object of the present invention to provide an improved method for forming semiconductor devices and for tailoring the electrical characteristics, of semiconductor devices such as the threshold voltage of select semiconductor devices. It is another object of the present invention to provide a method for tailoring the electrical characteristics of different regions of a semiconductor device such as raising the transistor Vt while minimizing any increase of junction capacitance of the source region relative to the drain region of a transistor. It is a further object of the present invention to provide a method for forming narrow width semiconductor devices that overcomes the "narrow width effect". It is a still further object of the present invention to provide a method for tailoring the electrical characteristics of select semiconductor devices that is efficient, low cost and adaptable to large scale semiconductor manufacture.